SmartNIC Architecture Unlocks Terabit Processing

Advancements in technology are relieving IO bottlenecks and ushering in a new era that will be dominated by Terabit computing for servers. Xilinx explores explores the benefits of adaptable SmartNIC architecture and how it will drive next generation data centers.

SmartNIC Architecture Unlocks Terabit Processing

A new white paper from Xilinx explores explores the benefits of adaptable SmartNIC architecture and how it will drive next generation data centers.

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Data center architecture has been changing at a rapid pace over the past few years. Advancements in technology are relieving IO bottlenecks and ushering in a new era that will be dominated by Terabit computing for servers.

According to Xilinx, these advancements mean that “server architecture is changing and the NIC (Network Interface Card) component has itself evolved to become a SmartNIC.” They go on to say that Smart NICs are “optimized to perform the first tier of application processing at wire speed, right at the network ingress/egress point.” No longer just a peripheral device, SmartNICs have graduated to being the “IO hub at the heart of the server.”

In the paper, Xilinx outlines their vision for SmartNIC. They say their technology is “a new vertically-integrated approach with the benefits of optimal per-bit processing efficiency and the removal of redundant data movement.”

In the paper, they explain four key things that their architecture enables, as well as some of the considerations that drive their vision for SmartNIC. Notably, they say that “hardware should not impose a fixed architecture on software, but that software should drive the generation and composition of the application specific data plane. We use high level languages to create these pipelines.”

“The old notion of a server containing network interfaces and application accelerators both as peripheral devices is dead and buried and the future lies in converged adaptive platforms.” – Xilinx, “How Adaptable SmartNICs Will Drive Next Generation Data Centers.”

Xilinx also discusses the importance of a portable NIC architecture. By utilizing P4, a high-level programming language, “the entire processing pipeline of the NIC itself is software-defined around a portable hardware scaffold.”

The paper also presents details on the Alveo SN1000, “Xilinx’s first SmartNIC to support the composable data plane and portable NIC architecture.”